Random telegraph noise (RTN) becomes quite important in small dimension devices, particularly in geometries with shorter interface (gate lengths). Our team works in the domain of RTN in advanced MOS devices. We have developed an algorithm to generate RTN using the concept of Poisson inter-arrival times by taking in values from industrial TCAD tools. To the best of knowledge, this algorithm is one of a kind of simulation-only model which generate RTN using noise spectral density profiles from TCAD simulation. We have utilized the RTN waveforms to create a random number generator (RNG).

Selected Work

• Deb, Deepjyoti, Goswami, Rupam, Baruah, Ratul Kr, "Random Telegraph Noise Due to Dielectric-Semiconductor Interface Traps in MOS Transistors", IEEE Transactions on Dielectrics and Electrical Insulation, Early Access, Nov. 2024.

Incomplete ionization is an important effect in semiconductors. However, its exploration has been negligible in the area of devices (applications of semiconductors). At TSDL, we have made attempts to understand the impact of incomplete ionization in advanced MOS devices such as TFETs using sensitivity as a parameter of analysis. 

Selected Work

• Pathak, Priyam, Deb, Deepjyoti, Nath, Dwipayan, Das, Prachuryya Subash, Choudhury, Hirakjyoti, Goswami, Rupam, "Incomplete Ionization-Dependent Carrier Mobility in Silicon-on-Insulator n-p-n Double-Gate Tunnel Field-Effect Transistors", Journal of Electronic Materials, vol. 42, pp. 1142–1160, Mar. 2024. ~ Editor's Choice ~

Memristors are at the heart of neuromorphic computing. At TSDL, we carry out fundamental research on the calibration of SPICE models for memristors, with emphasis on in-house fabricated biological memristors. We have calibrated multiple SPICE models for further analysis in digital computing applications.

Selected Works

• Choudhury, Hirakjyoti, Gogoi, Pallab Kr, Knaap, Ramon van der, Goswami, Rupam, Vanhamel, Jurgen, "Development of a SPICE Model for Fabricated PLA/Al/Egg Albumin/Al Memristors Using Joglekar's Approach", Electronics, vol. 14, no. 5, 838, Feb. 2025.

• Choudhury, Hirakjyoti, Gautam, Raja Vipul, Goswami, Rupam, Kumar, Vikas, "A SPICE model calibration framework for egg albumin memristors", Physica Scripta, vol. 100, no. 4, 45966, Mar. 2025.

• Choudhury, Hirakjyoti, Goswami, Rupam, Gautam, Raja Vipul, "Fabrication, Characterization and SPICE Calibration of Dropcasted Egg Albumin Memristors", 2024 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), Kolkata, India, 30 Nov. 2024 - 01 Dec. 2024, pp. 1-4.

• Choudhury, Hirakjyoti, Paul, Suvankar, Deb, Deepjyoti, Das, Prachuryya Subash, Goswami, Rupam, "A Single Memristor-based TTL NOT logic", Revista Tecnología En Marcha (Proceedings of IEEE Latin America Electron Device Conference, Puebla, Mexico, 03 - 05 July 2023), vol. 36, no. 6, pp. 88-94, June 2023. 

We make attempts at exploring the physics of different non-ideal effects like statistical variability studies of interface traps, impact of noise, and lateral straggle in TFETs and FinFETs.

Selected Works

• Lahkar, Himangshu, Medhi, Anurag, Deb, Deepjyoti, Saha, Rajesh, Baruah, Ratul Kr, Goswami, Rupam, "Statistical variability of physically localized interface traps in SOI n-p-n DG TFETs", Journal of Material Science: Materials in Electronics, vol. 36, 365 Feb. 2025.

• Das, Prachuryya Subash, Nath, Dwipayan, Deb, Deepjyoti, Pathak, Priyam, Choudhury, Hirakjyoti, Goswami, Rupam, "Mobility effects due to doping, temperature and interface traps in gate-all-around FinFETs", Microsystem Technologies, vol. 31, pp. 1089 - 1101, May 2025.

• Hazarika, Prajwalita, Ray, Mrigashree, Hazarika, Aditya, Deb, Deepjyoti, Das, Prachuryya Subash, Choudhury, Hirakjyoti, Goswami, Rupam, "Flatband voltage in MOS structures for spatial fixed oxide charge distributions", Journal of Materials Science: Materials in Electronics, vol. 34, no. 15, 1242, May 2023.

• Deb, Deepjyoti, Goswami, Rupam, Baruah, Ratul Kr, Saha, Rajesh, Kandpal, Kavindra, "Role of gate electrode in influencing interface trap sensitivity in SOI tunnel FETs", Journal of Micromechanics and Microengineering, vol. 32, no. 4, 44006, Mar. 2022.

• Deb, Deepjyoti, Goswami, Rupam, Baruah, Ratul Kr, Kandpal, Kavindra, Saha, Rajesh, "Parametric investigation and trap sensitivity of npn double gate TFETs", Computers and Electrical Engineering, vol. 100, 107930, May 2022.